1. Field of the Invention
The present invention relates to clock-data recovery (CDR), in particular to CDR that employs a time-interleaved scheme.
2. Description of Related Art
NRZ (non-return to zero) is a simple but widely used modulation scheme for representing a binary data stream by a voltage waveform suitable for transmission over a communication channel. For a binary data stream to be transmitted at a rate of R (in bits per second), the NRZ scheme represents a logical “1” data bit by a voltage pulse of a first level of duration T, and represents a logical “0” data bit by a voltage pulse of a second level of duration T, where T is the reciprocal of R. On the receiving end of the data transmission, a clock-data recovery (CDR) circuit is used to retrieve the binary data stream embedded in the voltage waveform.
FIG. 1A depicts a typical CDR circuit 100 that receives a voltage signal VIN and generates accordingly a recovered clock CLK and a retrieved binary data stream D embedded in the voltage signal VIN. CDR circuit 100 comprises: a sampler/phase-detector circuit 110 for generating the retrieved binary data stream D by sampling the voltage signal VIN using the recovered clock CLK, and also generating a phase signal, embodied by two logical signals UP and DN, to indicate a timing relationship between the voltage signal VIN and the recovered clock; a charge-pump (CP) circuit 120 for converting the two local signals UP and DN into a current signal IOUT; a loop filter (LF) 130 for converting the current signal IOUT into a control voltage signal VCON; and a VCO (voltage controlled oscillator) 140 for generating the recovered clock CLK under the control of the control voltage signal VCON. In a typical embodiment, when UP is asserted, a positive current pulse is generated by CP 120 to increase the control voltage VCON via LF 130; when DN is asserted, a negative current pulse is generated by CP 120 to decrease the control voltage VCO via LF 130. In a typical embodiment of VCO, increasing the control voltage VCON leads to speeding up the recovered clock CLK, while decreasing the control voltage VCON leads to slowing down the recovered clock CLK. When the sampler/phase-detector circuit 110 determines that the recovered clock is too fast (in reference to a timing embedded in the voltage signal VIN), it sets UP=0 and DN=1, indicating the voltage control signal VCON needs to be decreased to slow down the recovered clock CLK. When the sampler/phase-detector circuit 110 determines that the recovered clock is too slow (in reference to a timing embedded in the voltage signal VIN), it sets UP=1 and DN=0, indicating the voltage control signal VCON needs to be increased to speed up the recovered clock CLK. When the sampler/phase-detector circuit 110 is uncertain about the relative relationship between the recovered clock and the timing embedded in the voltage signal VIN, it sets UP=0 and DN=0, indicating the voltage control signal VCON needs to kept unchanged so that the recovered clock is neither sped up or slowed down. In this manner, the timing of the recovered clock is established in a closed-loop manner to track the timing embedded in the voltage signal VIN.
FIG. 1B depicts a typical sampler/phase-detector circuit 110 comprising: a first data flip-flop (DFF) 112 for sampling the voltage signal VIN at a rising edge of the recovered clock CLK to generate the retrieved data stream D; a second DFF 114 for sampling the retrieved data stream D at a rising edge of the recovered clock CLK to generate a delayed data stream F; a third DFF 116 for sampling the voltage signal VIN at a falling edge of the recovered clock CLK to generate a transitional data stream EN; a fourth DFF 118 for sampling the transitional data stream EN at a rising edge of the recovered clock CLK to generate a synchronized transitional data stream E; and a phase-detector logic circuit 119 for generating the two logical signals UP and DN based on the retrieved data stream D, the synchronized transitional data stream E, and the delayed data stream F, in accordance with a “binary phase detection” algorithm illustrated by the C-code shown in FIG. 1C.
To illustrate the principle of the “binary phase detection” algorithm, a typical timing diagram for sampler/phase-detector 110 is shown in FIG. 1D, if the waveforms of the voltage signal VIN, the retrieved data D, the delayed retrieved data F, the transitional data EN, and the synchronized transitional data F were to be observed using an oscilloscope. The waveform of the voltage signal VIN, generally referred to as an “eye diagram,” shows two distinct levels, representing the binary nature of the data embedded therein. The binary data embedded in the voltage signal VIN are labeled as Dn, Dn+1, Dn+2, and so on, where the subscripts represent time indices. Ideally, one would like the rising edge of the recovered clock CLK to align with the center of each data bit, where the “eye” has the greatest opening and the embedded data bits are most easily identified. In this case, the falling edge of the recovered clock CLK will align with data transition. When D is equal to F, the present retrieved data bit is the same as the previous (i.e. delayed) retrieved data bit. In this case, both UP and DN are set to 0, indicating the timing relationship between the voltage signal VIN and the recovered clock is uncertain. When D is not equal to F, the present retrieved data bit is different from the previous (i.e. delayed) retrieved data bit, indicating there is a transition in the voltage signal VIN. In this case, the synchronized transitional data bit E will either side with the present retrieved data bit D, or the previous retrieved data bit F. If E sides with D, it suggests the recovered clock is too slow, in reference with the timing embedded in the voltage signal VIN, and needs to be sped up (i.e. UP=1 and DN=0). If E sides with F, it suggests the recovered clock is too fast, in reference with the timing embedded in the voltage signal VIN, and needs to be slowed down (i.e. UP=0 and DN=1).
In another prior art, U.S. Pat. No. 6,442,225 uses multi-phase clock to eliminate dead-zone of phase detection. Although multiple phase detections are performed, they are used to detect the same data transition point. To be specific, if N=8 and the data rate is 1 data bit per second, then there are 8 phase detections per second using 8-phase 1-Hz clock. U.S. Pat. No. 6,442,225 aims to improve phase detection performance by using multiple phase detections per data transition.
While there are numerous alternative embodiments to sampler/phase-detector 110 in prior art, all embodiments involve using sampling devices such as data flip-flops or latches. When the data stream is to be transmitted at a very high rate (e.g. 10 Giga-bits per second or higher), the sampling devices also need to be operated at a very high rate, and the design may be very difficult to implement.
What is needed is method of a CDR technique that relaxes the requirement on the operational speed of the sampling devices.